Field of the Invention
The present invention relates to a forming method of forming a through electrode in a substrate, and a method of manufacturing an article.
Description of the Related Art
There is a method of forming a plurality of layers of circuit patterns overlaid when manufacturing a semiconductor device or the like. Japanese Patent Laid-Open No. 7-321012 describes a positioning method used when forming a plurality of layers of circuit patterns overlaid on one substrate.
A technique of manufacturing a semiconductor device by overlaying a plurality of substrates each including a circuit pattern has recently received attention. In this technique, a circuit pattern is formed on each of a plurality of substrates, and after that, the plurality of substrates are overlaid and joined. After the plurality of substrates are joined, a through electrode (Through Silicon Via; TSV) to electrically connect the circuit patterns of the substrates is formed in each substrate. For example, a through electrode to electrically connect the circuit pattern of a first substrate and the circuit pattern of a second substrate joined on the first substrate is formed in the second substrate.
However, when overlaying and joining a plurality of substrates, a position deviation of circuit pattern may occur between the plurality of substrates due to an overlay error between the plurality of substrates, deformation of the substrates caused by joint stress, and the like. If a through electrode is formed based on, for example, the marks (alignment marks) of the second substrate in a case where the position deviation has occurred, the through electrode may be prevented from contacting the circuit pattern (electrode pad) of the first substrate. In this case, the circuit pattern of the first substrate and that of the second substrate cannot be electrically connected.